1. Field of the Invention
The present invention relates to bus interfaces and more particularly to providing Inter-Integrated Circuit (I2C) protocol multiplexer switching as a function of clock frequency.
2. Description of the Related Art
Many similarities exist between seemingly unrelated designs in consumer, industrial and telecommunication electronics. Examples of similarities include intelligent control, general-purpose circuits (e.g., LCD drivers, I/O ports, RAM) and application-oriented circuits. The Inter-Integrated Circuit (I2C) bus is a bi-directional two-wire serial bus designed to exploit these similarities.
I2C buses can connect a number of devices simultaneously to the same pair of bus wires. Normally, the device addresses on the I2C bus are predefined by hardwiring on the circuit boards. A limitation of the I2C bus is that it will only allow a single device (e.g., an expansion board) to respond to each even address between 00 and FF. All addresses are even because only the high-order seven bits of the address byte are used for the address. Bit 0 is used to indicate whether the operation is to be a read or a write. Therefore, there are a limited number of addresses that can be assigned to a device.
With the I2C protocol, there is a limitation when mixing devices with different bit rate capacities in a parallel configuration. To avoid this issue, hardware developers can use a switch to isolate fast and standard devices and a general purpose input/output (GPIO) bus expander to control when the switch is opened. Although in some cases this solution will work, this solution still requires the I2C master to have knowledge of the I2C topology in order to keep track of flipping a multiplexer or switch in order to communicate with the correct port. Moreover, such I2C multiplexers require the use of an I2C address.